1. Field of the Invention
Generally, the present disclosure relates to the field of plasma etching, and, more particularly, to plasma etching of an interlayer dielectric during semiconductor device manufacturing.
2. Description of the Related Art
The fabrication of complex integrated circuits requires the provision of a large number of transistor elements, which are used in logic circuits as efficient switches and which represent the dominant circuit element for designing circuits. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as micro-processors, storage chips and the like, CMOS technology is currently the most promising approach due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. In CMOS circuits, complementary transistors, i.e., P-channel transistors and N-channel transistors, are used for forming circuit elements, such as inverters and other logic gates to design highly complex circuit assemblies, such as CPUs, storage chips and the like. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. After completing the formation of the active components, e.g., transistors, capacitors or resistors, the wafer is usually sealed with a layer of a dielectric material, e.g., silicon dioxide (SiO2). Via holes are formed in the dielectric material which are filled with a suitable metal, e.g., tungsten and tantalum, thereby forming metal plugs which provide electrical connections to the contacts of the individual components. The process sequence up to this point is sometimes called “Front End of Line” (FEL) process sequence. Thereafter, the components are usually tested to ensure correct operation of the components.
The individual components, e.g., transistors, require electrical interconnections which provide the final functionality of the desired units, e.g., chips, which include the individual components. The process sequence for formation of the electrical interconnections between the components is sometimes called “Back End of Line” (BEOL) process sequence. Usually, the electrical interconnections are formed by a series of conductive layers which are separated by dielectric layers. The dielectric layers are often referred to as “InterLayer Dielectric” (ILD).
Common materials for interlayer dielectric layers comprise silicon-based oxide materials that serve as electrical insulators, e.g., undoped silicon oxide, fluorine-doped silicon oxide and other materials. Other interlayer dielectric materials include low-k dielectrics, i.e., insulating materials with a low dielectric constant, e.g., materials with a k-value less than 3. Low-k dielectrics include silicon-based materials as well as carbon-based materials, polymer materials and the like.
The increasing level of integration of integrated circuits has also resulted in an increase in the number of layers that make up the integrated circuit. Up to ten interconnection layers or more may be provided. However, as the number of layers in the integrated circuit continues to increase, advanced processes are being developed in order to reduce the number of process steps which are necessary for one functional layer. These advanced processes often demand extraordinary properties of the chemistry of the etching process. Etching stacked dielectric layers is one of the most difficult demands.
The individual interconnection layers are electrically connected by conductive plugs, as described above, which are formed in respective via holes in the dielectric layers. Different methods for providing the electrical interconnections are commonly used. One method is to fill not only the via holes but to provide a continuous metal layer of the respective metal over both the filled via holes and the dielectric. Thereafter, a lithographic step is used to define a photoresist layer over the planar metal layer and respectively etch the exposed metal. In this way, a network of electrical interconnects is obtained. Another method, called damascene process, uses chemical mechanical polishing instead of metal etching. This is particularly advantageous for copper interconnects, since the etch products obtained by copper etching are less volatile than respective etch products obtained by silicon or aluminum etching. In the damascene process, in addition to the via holes, recesses for the electrical interconnections are formed in the dielectric layer. The via holes as well as the recesses corresponding to the electrical interconnections are filled with the desired metal and afterwards the surface is planarized by chemical mechanical polishing (CMP).
In order to obtain a desired high packing density, a small diameter of the via holes is desirable. However, since the thickness of the dielectric layer must be reasonably thick to minimize the ILD capacitance, the via holes in modern integrated circuits are formed exhibiting an aspect ratio that may be as high as approximately 8:1 or more, and the opening may have a diameter of 0.1 μm or smaller. The aspect ratio of such openings is generally defined as the ratio of the depth of the opening to the width of the opening. Such high aspect ratios require a reliable etch process with high accuracy.
The via holes are usually formed by a highly anisotropic etch process, e.g., a plasma etch process. Generally, a plasma etch process comprises providing process gases which form, at a suitable process temperature, gaseous compounds with the material to be etched. Usually the process gases do not react spontaneously with the material to be etched. Rather, a plasma is provided in which the process gases dissociate into reactive free radicals which do react spontaneously to form volatile compounds. For a dielectric etch, in particular for a silicon dioxide (SiO2) etch, plasma etch processes on the basis of carbon-fluorine-process gases, referred to as fluorocarbon in the following, are well established. Plasma sources of various kinds are known, including capacitively coupled plasma etchers. Herein, at least two electrodes are provided in a chamber with the wafer to be etched therebetween. To one electrode, e.g., to a lower electrode, an alternating current power, typically a radio frequency (RF) power, is applied for generating and maintaining a plasma in the chamber. Further, a bias power is applied over the electrodes, leading to a directional bombardment of the wafer with the ions generated from the precursor gases. Another type of plasma etcher is a inductively coupled plasma etcher, wherein the plasma in the chamber is generated by generating an alternating electromagnetic field in the chamber by applying a respective current to a coil.
In order to obtain a well-defined etch result, etch stop layers are usually provided below the dielectric layer which is subjected to plasma etching. The etch stop layer has a composition relative to the dielectric layer such that an etch chemistry is available which effectively etches a vertical hole in the overlying dielectric layer but stops on the etch stop layer. In other words, the etch process selectively etches the dielectric layer over the etch stop layer. Advanced semiconductor devices comprise a dielectric layer of, e.g., undoped silicon oxide, non-stoichiometric materials SiOx, doped silica glasses such as fluorinated silica glass (FSG), e.g., F-TEOS, which exhibits much the same chemistry as silicon dioxide (SiO2), low-k dielectrics and the like. A suitable stop layer material for oxides like silicon dioxide (SiO2) is silicon nitride, e.g., Si3N4 or non-stoichiometric ratios SiNx with x between 1.0 and 1.5, may be suitable.
In the plasma etch process, besides the volatile compound formed of the material to be etched and the respective precursor, polymers may form from the process gases, e.g., CxFy fragments may form fluorocarbon polymers. The well-defined formation of polymers may be used to advantage to optimize the etch process. However, even undesired side reactions may lead to the formation of polymers in the etched via hole which may interfere with a conductive material subsequently filled in the via hole. After the etching of via holes is completed, the resist mask must be removed, which may constitute an additional source of residual polymer material left within the etched via. It is common practice in plasma etching via holes to include a post-etch treatment (PET) step to minimize the residual polymer material left within the via hole.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.